In Intel Corporation v. Pact XPP Schweiz AG, the Court of Appeals for the Federal Circuit (“Federal Circuit”) reversed and remanded the decision of the Patent Trial and Appeal Board (“Board”). In the decision, the Federal Circuit rejected the Board’s rigid application of the “motivation-to-combine” analysis that required an element from one reference must provide an improvement to another reference to justify the combination. Instead, the Federal Circuit held that the “motivation-to-combine” analysis simply required showing that a proposed combination would help resolve an issue and be within the capabilities of a person of ordinary skill in the art (“POSITA”).
Intel Corporation (“Intel”) petitioned for inter partes review (IPR) of claims 4 and 5 of U.S. Patent No. 9, 250, 908 (“the ’908 patent”) held by Pact XPP Schweiz AG (“PACT”). Claim 4 of the ’908 patent taught a multiprocessor system that used a separated cache and interconnect system that interconnected each of the separated cache segments with each of the processors, each of the processors with neighboring processors, and each of the separated cache segments with neighboring separated cache segments.
Intel argued that it would have been obvious to a POSITA to combine two prior art references (“Kabemoto”) and (“Bauman”) to teach all the limitations of claim 4 under a “known-technique” rational. In particular, Intel reasoned that a POSITA “would have naturally turned to Bauman’s segmented cache to use … in Kabemoto: since Bauman’s separated cache was known to address the same cache-coherence issue that Kabemoto also sought to address.”
PACT did not dispute that the combined references disclosed all the limitations of the ’908 patent, but instead argued that Intel had failed to show that a POSITA would have been motivated to combine the references.
The Board concurred: “If … Kabemoto already addresses [the] problem through the use of a known technique similar to that of Bauman’s, [it] fail[ed] to see why one of ordinary skill in the art would regard Bauman’s technique as an obvious improvement to Kabemoto.”
Thus, the Board, in its final written decision, agreed with PACT that Intel had failed to show a proper motivation to combine the prior art.
On appeal, Intel argued the Board’s determination that there was no motivation to combine the teachings of Kabemoto and Bauman to reach the limitations of claim 4 lacked substantial evidence; the Federal Circuit agreed holding that the Board had misapplied the standard.
Under the “known-technique” rational, “if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill.” Accordingly, the Federal Circuit held that a proposed combination does not have to be the best option but can merely be a suitable option in order to satisfy a “motivation-to-combine” analysis.
Thus, Intel never had to show that replacing Kabemoto’s secondary cache with Bauman’s secondary cache constituted an improvement. Rather, it was sufficient for Intel to show that there was a known problem of cache coherency in the art, Bauman’s secondary cache helped address the issue, and combining the teachings of Kabemoto and Bauman was not beyond the capabilities of a POSITA. Accordingly, the Federal Circuit reversed the Board’s factual findings and remanded to the Board to address any remaining dispute about the patentability of claim 5.
A “motivation-to-combine” analysis does not require showing the combination constitutes an “improvement.” All that is required to be shown is that the combination could help address an issue and is within the scope of a person of ordinary skill in the art.